Shallow trench isolation (STI) is a common semiconductor process employed to isolate two neighboring portions of a substrate or structure formed thereon. STI can be carried out, for example, early on in the fabrication of a semiconductor device prior to the formation of transistors or other components, such as on a blank substrate. STI can also be carried out at some later time in the fabrication process when at least some portion of a semiconductor structure is formed.
STI generally includes etching one or more trenches in the substrate (such as a blank substrate, or a partially completed semiconductor structure such as quantum well growth structure), and then depositing dielectric materials (such as silicon dioxide) to fill the trenches. The excess dielectric material can then be removed using chemical-mechanical planarization (CMP).
STI may be employed to isolate two neighboring portions of a substrate or structure formed thereon. Those neighboring portions may include transistors or other circuit components.
One such transistor includes a conventional metal oxide semiconductor field effect transistor (MOSFET), where the source, channel, and drain structures are constructed adjacent to each other within the same plane. The gate dielectric is formed on the channel area and the gate electrode is deposited on the gate dielectric. The transistor is controlled by applying a voltage to the gate electrode thereby allowing a current to flow through the channel between source and drain. The area necessary to support these structures in a plane constrains the number of transistors that can be placed within the limited area of a semiconductor chip. Semiconductor manufacturers increase the packing density of transistors by scaling down the size of the transistor at each generation of technology.
A tri-gate transistor, or non-planar transistor, allows for greater packing density of transistors. A tri-gate transistor includes a thin semiconductor body (e.g., a silicon fin) formed on a substrate and having a top surface and two sidewall surfaces perpendicular (or almost perpendicular) to the top surface. A gate structure is formed on the substrate and the silicon fin perpendicular to the silicon fin. Source and drain regions are formed in the fin on opposite sides of the gate structure. Because the gate structure surrounds the silicon fin on the three surfaces, the transistor essentially has three separate gates. These three separate gates provide three separate channels for electrical signals to travel, thus effectively tripling the conductivity as compared to a conventional planar transistor.